SANTA CLARA, USA: Agilent Technologies Inc. has introduced the industry’s fastest logic analyzer. The new instrument combines an industry-leading state capture speed of 4 Gb/s on 68 channels and 2.5 Gb/s on 136 channels with the ability to reliably capture data on the industry’s smallest eye openings, as small as 100 ps by 100 mV. These capabilities allow engineers to measure the increasingly fast digital signals used in emerging technologies and validate and troubleshoot their designs with confidence.
The Agilent U4154A AXIe-based logic analyzer module and associated probes and powerful analysis software provide essential capabilities for engineers working with DDR (double data rate) memory systems, high-speed application-specific integrated chips, analog-to-digital converters and field-programmable gate arrays operating at speeds up to 4 Gb/s.
Timing zoom provides simultaneous state and timing measurements with 80 ps timing resolution and 256 K-sample memory depth, which gives designers more insight into problems by allowing simultaneous state and high-resolution timing measurements over a 20-us time span. The industry’s highest trigger sequencer speed (2.5 Gb/s) gives engineers the ability to trigger reliably on sequential events on DDR memory and other high-speed signals without having to give up triggering flexibility.
“The need for reliable measurements and deep analysis has reached a critical juncture as engineers who focus on high-performance servers and embedded systems begin work on DDR3 2133 systems,” said Perry Keller, Agilent’s representative on the JEDEC DDR committee. “These capabilities will become more critical in the near future as DDR memory speeds continue to increase. The U4154A logic analyzer is the ideal tool for DDR memory measurement and debug work.”
At high speeds, signal integrity validation becomes critical for reliable performance. Validating signal integrity on all channels of a DDR system with an oscilloscope can be very time consuming. The exclusive eye-scan capability of the U4154A allows a quick overview of signal integrity on all signals of a DDR system in a fraction of the time it takes using alternative methods.